1. Field of the Invention
The present invention relates a semiconductor apparatus and a method for manufacturing the semiconductor apparatus. Particularly, the present invention relates a semiconductor apparatus including a plurality of stacked semiconductor chips and a method for manufacturing the semiconductor apparatus.
2. Description of Related Art
With rapid development of smaller and more sophisticated electronic equipment, demand for highly integrated semiconductor apparatus is increasing. In order to achieve higher integration of semiconductor apparatus, technologies such as System-On-Chip (SOC) and System in Package (SIP) are used. The SOC technology incorporates a plurality of functions into one semiconductor chip. The SIP technology stacks a plurality of semiconductor chips on one another and packages them in one semiconductor apparatus.
Because of process miniaturization of high integration and high density semiconductor apparatus into submicrons, the effect of signal integrity or signal waveform quality becomes more important. Low signal integrity causes problems such as crosstalk due to signal degradation and voltage drop or IR drop, which gives adverse effects to the operation of the semiconductor apparatus.
A semiconductor apparatus with Chip-On-Chip (COC) technology, which is one type of the SIP technology, includes two semiconductor chips bonded together by face-down bonding with their circuit surfaces facing each other. This specification uses the term “circuit surface” of a semiconductor chip to refer to the surface where a circuit such as LSI is formed, and “bottom surface” of a semiconductor chip to refer to the surface that is the reverse side of the circuit surface.
FIG. 5 is a schematic cross-sectional view of a conventional COC type semiconductor apparatus. This semiconductor apparatus 100 has a package substrate 110, a lower semiconductor chip 120, and an upper semiconductor chip 130.
The lower semiconductor chip 120 is placed on a mounting surface of the package substrate 110. This specification uses the term “mounting surface” of a package substrate to refer to the surface where a semiconductor chip is mounted, and “bottom surface” of a package substrate to refer to the surface that is the reverse side of the mounting surface.
A package external terminal 111 such as a solder ball is formed on the bottom surface of the package substrate 110. Lines and through holes are formed inside the package substrate 110.
In the lower semiconductor chip 120, a lower chip internal line 121 such as a multilayer thin film line is formed on the circuit surface, and a lower external terminal 122 such as a pad is formed in the peripheral part of the circuit surface. Further, an internal circuit and a lower internal terminal are formed in the central part of the circuit surface of the lower semiconductor chip 120, though not shown.
In the upper semiconductor chip 130, an upper external terminal 131 is formed in the peripheral part of the circuit surface. Further, an internal circuit and an upper internal terminal are formed in the central part of the circuit surface of the upper semiconductor chip 130, though not shown.
The package external terminal 111 and a line on the mounting surface of the package substrate 110 are electrically connected via a through hole or the like inside the package substrate 110. The line on the mounting surface of the package substrate 110 and the lower external terminal 122 are electrically connected by a bonding wire 123. The lower chip internal line 121 and the upper external terminal 131, and a lower internal terminal and an upper internal terminal are respectively electrically connected to each other via a bump 124.
The semiconductor apparatus 100 supplies power to the package external terminal 111 to activate internal circuits of the lower semiconductor chip 120 and the upper semiconductor chip 130. The power is supplied to the internal circuit of the lower semiconductor chip 120 through the package external terminal 111 and the lower external terminal 122. The power is supplied to the internal circuit of the upper semiconductor chip 130 through the package external terminal 111, the lower external terminal 122, the lower chip internal line 121, the bump 124, and the upper external terminal 131.
Hence, the power whose voltage is dropped by the resistance of the lower chip internal line 121 or the like is supplied to the internal circuit of the upper semiconductor chip 130. Thus, the effect of the signal integrity is more significant on power supply to the internal circuit of the upper semiconductor chip 130 than on power supply to the internal circuit of the lower semiconductor chip 120.
With the miniaturization in the semiconductor process, current consumption of a single chip increases, and power supply voltage drop, which is determined by the product of a consumption current and a power line resistance, increases accordingly. Thus, a decrease in power supply voltage drop is required.
Further, with a decrease in the size of a logic chip and an increase in the capacity of a memory to be mounted, cases that use a logic chip for the upper semiconductor chip 130 and a memory chip for the lower semiconductor chip 120, instead of using a memory chip for the upper semiconductor chip 130 and a logic chip for the lower semiconductor chip 120, are increasing. In such cases, power supply voltage drop significantly affects the operation of the logic chip.
Further, since a rated drive voltage decreases with the decrease in the size of a logic chip, the sensitivity for power supply voltage drop becomes higher. This results in a decrease in the power consumption value allowed in the peripheral pad configuration that makes an electrical connection from a peripheral pad to a package external terminal such as the semiconductor apparatus 100. This imposes more severe restriction on the power consumption for a single chip due to voltage drop.
The COC structure such as the semiconductor apparatus 100 needs to supply all the consumption power to the upper and lower semiconductor chips from the lower external terminal 122 of the lower semiconductor chip 120. It is thereby difficult to take measures to suppress the voltage drop at the single chip level.
Particularly, the power is supplied to the upper semiconductor chip 130 through the lower chip internal line 121 between the lower external terminal 122 and the upper external terminal 131. The lower chip internal line 121 is formed by a semiconductor chip fabrication process and has higher resistance than a bonding wire or the like. Thus, it is required to consider the voltage drop occurring in the lower chip internal line 121 in addition to the voltage drop occurring in a single chip of the upper semiconductor chip 130.
Further, power supply inductance increases due to the lower chip internal line 121, and a simultaneous switching noise determined by the product of inductance and current shift increases accordingly. This causes a lower operation speed and circuit malfunction.
A semiconductor apparatus with the COC technique is described in Japanese Unexamined Patent Application Publication No. 2003-17655, for example. This semiconductor apparatus, however, forms an insulation layer on the circuit surface of a semiconductor chip in a semiconductor packaging process.
As described in the foregoing, the present invention has recognized that a conventional semiconductor apparatus that packages a plurality of semiconductor chips stacked on one another is affected by signal integrity more significantly than the configuration with a single semiconductor chip, causing power supply voltage drop. Further, the power supply voltage drop causes lower operation speed and malfunction and reduces power consumption allowance. Furthermore, an increase in the inductance of a power supply line leads to a higher simultaneous switching noise.